Memory Circuity and Dynamic Random Access Memory Circuity Memory Circuity and Dynamic Random

ABSTRACT

A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area. Area peripheral to the well includes memory peripheral circuitry area. A plurality of memory cell storage capacitors is received within the well over the word lines. Peripheral circuitry is received within the peripheral circuitry area and is operatively configured to write to and read from the memory array.

TECHNICAL FIELD

[0001] This invention relates to memory circuitry and to methods offorming memory circuitry.

BACKGROUND OF THE INVENTION

[0002] Memory circuitry in semiconductor fabrication is formed toinclude an array area where individual memory cells are typicallyfabricated in a dense repeating pattern, and a peripheral area whereperipheral circuitry which is operatively configured to write to andread from the memory array is fabricated. Peripheral circuitry and arraycircuitry are typically largely fabricated at the same time. Further thememory cell capacitors within the memory array are commonly fabricatedto be vertically elongated, sometimes in the shape of cups orcontainers, in order to maximize the available surface area forindividual capacitors for storage capacitance. The electronic componentsor devices of the peripheral circuitry are not typically as verticallyelongated, thereby creating topography problems in the fabrication dueto portions of the memory array circuitry being fabricated significantlyelevationally higher than portions of the peripheral circuitry.

[0003] The invention was principally motivated in addressing orovercoming problems associated with this issue, and in the fabricationof capacitor-over-bit line dynamic random access memory circuitry.However, the invention is in no way so limited, and is applicablewithout limitation to these problems or objectives, with the inventiononly being limited by the accompanying claims appropriately interpretedin accordance with the doctrine of equivalents.

SUMMARY

[0004] The invention comprises memory circuitry and methods of formingmemory circuitry. In but one implementation, a method of forming memorycircuitry having a memory array having a plurality of memory capacitorsand having peripheral memory circuitry operatively configured to writeto and read from the memory array, includes forming a dielectric wellforming layer over a semiconductor substrate. A portion of the wellforming layer is removed effective to form at least one well within thewell forming layer. An array of memory cell capacitors is formed withinthe well. The peripheral memory circuitry is formed laterally outward ofthe well forming layer memory array well.

[0005] In one implementation, a dielectric well forming layer is formedover a semiconductor substrate. A portion of the well forming layer isremoved effective to form at least one well within the well forminglayer. A capacitor storage node forming layer is formed within the well.An array of capacitor storage node openings is formed within thecapacitor storage node forming layer within the well. Capacitor storagenode electrodes are formed within the capacitor storage node forminglayer openings. After forming the capacitor storage node electrodes, atleast some of the capacitor storage node forming layer is removed fromwithin the well. Peripheral memory circuitry is formed laterally outwardof the well.

[0006] In one implementation, memory circuitry includes a semiconductorsubstrate. A plurality of word lines is received over the semiconductorsubstrate. An insulative layer is received over the word lines and thesubstrate. The insulative layer has at least one well formed therein.The well has a base received over the word lines. The well peripherallydefines an outline of a memory array area. Area peripheral to the wellincludes memory peripheral circuitry area. A plurality of memory cellstorage capacitors is received within the well over the word lines.Peripheral circuitry is received within the peripheral circuitry areaand is operatively configured to write to and read from the memoryarray.

[0007] Other implementations are contemplated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0009]FIG. 1 is a diagrammatic sectional view of a semiconductor waferfragment at one processing step in accordance with an aspect of theinvention.

[0010]FIG. 2 is a diagrammatic sectional view of the FIG. 1semiconductor wafer fragment at the one processing step of FIG. 1 buttaken through a different section of the wafer fragment.

[0011]FIG. 3 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that depicted by FIG. 1.

[0012]FIG. 4 is a top plan view of the FIG. 3 wafer fragment.

[0013]FIG. 5 is a view of the FIG. 3 wafer fragment at a processing stepsubsequent to that depicted by FIG. 3.

[0014]FIG. 6 is a view of the FIG. 5 wafer fragment at a processing stepsubsequent to that depicted by FIG. 5.

[0015]FIG. 7 is a view of the FIG. 6 wafer fragment at a processing stepsubsequent to that depicted by FIG. 6.

[0016]FIG. 8 is a view of the FIG. 7 wafer fragment at a processing stepsubsequent to that depicted by FIG. 7.

[0017]FIG. 9 is a view of the FIG. 8 wafer fragment at a processing stepsubsequent to that depicted by FIG. 8.

[0018]FIG. 10 is a view of the FIG. 9 wafer fragment at a processingstep subsequent to that depicted by FIG. 9.

[0019]FIG. 11 is a view of the FIG. 10 wafer fragment at a processingstep subsequent to that depicted by FIG. 10.

[0020]FIG. 12 is a view of the FIG. 11 wafer fragment at a processingstep subsequent to that depicted by FIG. 11.

[0021]FIG. 13 is a view of the FIG. 12 wafer fragment at a processingstep subsequent to that depicted by FIG. 12.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0023] Referring initially to FIGS. 1 and 2, a semiconductor substratein the form of a wafer fragment is indicated generally with referencenumeral 10. In the context of this document, the term “semiconductorsubstrate” or “semiconductive substrate” is defined to mean anyconstruction comprising semiconductive material, including, but notlimited to, bulk semiconductive materials such as a semiconductive wafer(either alone or in assemblies comprising other materials thereon), andsemiconductive material layers (either alone or in assemblies comprisingother materials). The term “substrate” refers to any supportingstructure, including, but not limited to, the semiconductive substratesdescribed above. Further in the context of this document, the term“layer” encompasses both the singular and the plural.

[0024] In only a preferred embodiment, dynamic random access memorycircuitry is fabricated and described. Semiconductor wafer fragment 10comprises a bulk monoctystalline substrate 12 having an array of wordlines 14 formed thereover. Such are shown as comprising a gate oxidelayer 16, an overlying conductively doped polysilicon layer 18, anoverlying silicide layer 20, and an insulative cap 22. Anisotropicallyetched insulative sidewall spacers 23 are received about word lines 14.Capacitor storage node plugs 24 are received between the illustratedword lines, and constitute exemplary storage node contact locations aswill be apparent from the continuing discussion. An array of digit lines26 (FIG. 2) is formed over word lines 14. An insulative layer 29 isreceived between digit lines 26 and substrate 12, and exposes a digitline contact location 28 between the middle two illustrated word lines.An example material for layer 29 is undoped SiO₂ deposited bydecomposition of tetraethylorthosilicate. An exemplary thickness is fromabout 300 Angstroms to about 500 Angstroms. Suitable source/drainconstructions (not shown) would be provided relative to substrate 12 asis conventional, or as might be developed in later generationtechnologies.

[0025] A dielectric well forming layer 30 is formed over semiconductorsubstrate 12 over word lines 14 and bit lines 26. An example preferredmaterial includes doped silicon dioxide, such as borophosphosilicateglass (BPSG) deposited to an exemplary thickness range of from about10,000 Angstroms to about 30,000 Angstroms, and is preferably composedto consist essentially of a doped silicon dioxide. Preferably, as shown,such comprises an outer planar surface 32.

[0026] Referring to FIGS. 3 and 4, a portion of dielectric/insulativewell forming layer 30 is removed to form at least one well 34 withinwell forming layer 30. Such patterning and removal most preferablyoccurs by photolithography whereby the area outside of well portion 34is masked with photoresist, and a timed etched is preferably thenconducted of layer 30 using a chemistry substantially selective to notremove the photoresist to form the illustrated well 34. Well 34 includesa periphery 35, which peripherally defines an outline of a memory arrayarea and an area 36 peripheral and laterally outward of well 34 whichcomprises memory peripheral circuitry area. Well 34 also includes a base38 which, in the preferred illustrated embodiment, is substantiallyplanar. The etch to produce to the illustrated well 34 is preferablytimed to provide a lowestmost portion 38 thereof which is received aboveword line caps 22 by at least 2000 Angstroms. Further, lowestmostportion 38 is preferably received above outermost tops of digit lines 26by at least 1000 Angstroms and preferably less than 4000 Angstroms. Amore preferred distance between base 38 and the outermost tops of thedigit lines is from about 2500 Angstroms to about 3500 Angstroms, with3000 Angstroms being a specific preferred distance.

[0027] Referring to FIG. 5, an etch stop layer 39 (preferablydielectric) is preferably deposited over well forming layer 30 outwardof and to within well 34 to less than completely fill well 34. Anexemplary and preferred material for layer 39 is silicon nitride, withan exemplary preferred deposition thickness being from about 40Angstroms to about 125 Angstroms, with from about 50 Angstroms to 70Angstroms being more preferred. Such provides an insulative layer 39/30outermost surface 40 which, in the illustrated and preferred embodiment,is substantially planar laterally outside of well 34.

[0028] Referring to FIG. 6, a storage node forming layer 42 is formedover etch stop layer 39 laterally outward of and to within well 34 tooverfill well 34. Layer 42 preferably comprises a dielectric material,with BPSG being but one example. In the depicted embodiment, storagenode forming layer 42 is initially formed to be substantiallynon-planar.

[0029] Referring to FIG. 7, storage node forming layer 42 is planarized.Preferably, the planarization is such to be effective to leave etch stoplayer 39 covered by storage node forming layer 42 of a thickness of atleast about 1,000 Angstroms outside of well 34. Planarization mightoccur by resist-etch back, chemical-mechanical polishing, or any otherexisting or yet-to-be-developed planarizing technique.

[0030] Referring to FIG. 8, an array of capacitor storage node openings44 is formed through storage node forming layer 42, through etch stoplayer 39, and into well forming layer 30 through well base 38 withinwell 34. Storage node openings 44 are formed over storage node contactlocations/plugs 24.

[0031] Referring to FIG. 9, a capacitor storage node layer 46(preferably hemispherical grain polysilicon, HSG) is formed preferablybe chemical vapor depositing over storage node forming layer 42 towithin capacitor storage node openings 44 to less than completely fillsuch openings.

[0032] Referring to FIG. 10, capacitor storage node layer material 46has been removed outwardly of storage node forming layer 42 effective toform an array of storage node capacitor electrodes 47 in electricalconnection with storage node contact locations/plugs 24. In theillustrated, and preferred embodiment, storage node capacitor electrodes47 comprise a portion which has a container shape, with the portionbeing formed to be partially received within well forming layer 30through the base openings within well 34. Non-container capacitorelectrode constructions are also of course contemplated. Removal canoccur by any of a number of techniques, with chemical-mechanicalpolishing being preferred. Capacitor storage node containers 47 havetopmost surfaces 48 which, in the preferred embodiment, are receivedelevationally proximate outermost surface 40 of insulative layer 39/30.In the context of this document, “elevationally proximate” meanselevationally within 50 Angstroms. In the illustrated and preferredembodiment, topmost surfaces 48 are received elevationally abovesubstantially planar outermost surface 40 by less than 50 Angstroms. Inpreferred embodiments, exactly elevationally coincident or elevationallybelow are also contemplated, although not as preferred as that depictedin the drawings.

[0033] Referring to FIG. 11, at least some of capacitor storage nodeforming layer 42 is removed from within well 34. Preferably, suchremoval occurs by chemical etching using a chemistry which issubstantially selective to remove capacitor storage node forming layer42 relative to etch stop layer 39, and as well exposes lateral outercontainer surface area 49 of capacitor containers 47. As illustrated andpreferred, substantially all of capacitor storage node forming layer 42is shown as having been etched from the substrate using dielectric etchstop layer 39 as an etch stop. Where layer 42 comprises BPSG and layer39 comprises silicon nitride, an exemplary chemistry is dilute HF at a10:1 volume ratio.

[0034] Referring to FIG. 12, a capacitor dielectric layer 50 and acapacitor cell electrode layer 52 are formed over capacitor storage nodecontainers 47, including outer surface area 49.

[0035] Such provides but one example of forming an array of memory cellcapacitors within well 34 over word lines 14 and digit lines 26.Peripheral circuitry 55 is formed within peripheral circuit area 36 and16 is operatively designed and configured to write to and read from thememory array, as is conventional or as yet-to-be-developed. Exemplaryexisting peripheral dynamic random access memory circuitry includessense amplifier elements, equilibration and bias circuits, isolationdevices, input/output transistors, etc. Exemplary devices 55 are shownonly diagrammatically, as the peripheral circuitry placement, not theactual circuitry itself, is only what is germane to aspects of thisinvention.

[0036] Referring to FIG. 13, a planarized dielectric layer 56 andexemplary metal line/wiring components 58 are shown as being fabricated.

[0037] The illustrated exemplary embodiment, by way of example only andin no way by way of limitation, effectively elevationally recesses thememory array and thereby the vertically elongated memory arraycapacitors compared to the memory peripheral circuitry area. The outersurface of insulative layer 39/30 thereby provides a base which ispreferably elevationally proximate or coincident with the tops of thestorage nodes of the memory cell capacitors upon or through which theperipheral circuitry can be fabricated.

[0038] Further, the illustrated exemplary embodiment, by way of exampleonly and not by way of limitation, also facilitates prevention of anexisting processing problem known as oxidation punch-through.Punch-through results from oxygen penetration into lower substrate areasduring wafer fabrication and undesired oxidation of underlyingconductive components. Prior art capacitor fabrication methods havetypically contended with punch-through by the silicon nitride barrierfunction of the capacitor dielectric material which typically comprisesat least part of the capacitor dielectric layer. The nitride serves as abarrier to oxygen diffusion in subsequent steps which can undesirablyform insulative oxides on circuitry material. Yet existing designscontinue to push the effective thickness of the capacitor dielectricsilicon nitride layer ever thinner such that suitable nucleation allover the wafer and barrier properties typically will not occur. In theillustrated preferred embodiment, etch stop layer 39 is ideallyfabricated of a diffusion barrier material, such as silicon nitride, andcan be deposited to a suitable thickness (i.e., at least 50 Angstroms)to desirably form both an etch stop barrier layer function and an oxygendiffusion barrier layer during circuitry fabrication.

[0039] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming memory circuitry comprising a memory array havinga plurality of memory capacitors and comprising peripheral memorycircuitry operatively configured to write to and read from the memoryarray, comprising: forming a dielectric well forming layer over asemiconductor substrate; removing a portion of the well forming layereffective to form at least one well within the well forming layer;forming an array of memory cell capacitors within the well; and formingthe peripheral memory circuitry laterally outward of the well forminglayer memory array well.
 2. The method of claim 1 wherein the wellforming layer consists essentially of doped silicon dioxide.
 3. Themethod of claim 1 wherein the well has a well base which issubstantially planar.
 4. The method of claim 1 wherein the semiconductorsubstrate comprises word lines having insulative caps and the well has awell base, the removing leaving a lowest portion of the well base atleast 2000 Angstroms above the caps.
 5. The method of claim 1 whereinthe capacitors respectively comprise a portion which has a containershape.
 6. The method of claim 1 wherein the capacitors respectivelycomprise a portion which has a container shape, the portion being formedto be partially received within the well forming layer beneath the well.7. A method of forming memory circuitry comprising a memory array havinga plurality of memory capacitors and comprising peripheral memorycircuitry operatively configured to write to and read from the memoryarray, comprising: forming a dielectric well forming layer over asemiconductor substrate; removing a portion of the well forming layereffective to form at least one well within the well forming layer, thewell having a well base; forming an array of capacitor storage nodeopenings through the well base into the well forming layer over storagenode contact locations; supporting an array of storage node capacitorelectrodes within the well and base openings therein by the well forminglayer; and forming the peripheral memory circuitry laterally outward ofthe well forming layer memory array well.
 8. The method of claim 7wherein the well base is substantially planar.
 9. The method of claim 7wherein the semiconductor substrate comprises word lines havinginsulative caps, the removing leaving a lowest portion of the well baseat least 2000 Angstroms above the caps.
 10. The method of claim 7wherein the capacitors respectively comprise a portion which has acontainer shape, the portion being formed to be partially receivedwithin the well forming layer beneath the well base.
 11. A methodof-forming memory circuitry comprising a memory array having a pluralityof memory capacitors and comprising peripheral memory circuitryoperatively configured to write to and read from the memory array,comprising: forming a dielectric well forming layer over a semiconductorsubstrate; removing a portion of the well forming layer effective toform at least one well within the well forming layer; forming acapacitor storage node forming layer within the well; forming an arrayof capacitor storage node openings within the capacitor storage nodeforming layer within the well; forming capacitor storage node electrodewithin the capacitor storage node forming layer openings; after formingthe capacitor storage node electrodes, removing at least some of thecapacitor storage node forming layer from within the well; and formingthe peripheral memory circuitry laterally outward of the well.
 12. Themethod of claim 11 comprising forming an etch stop layer within the wellprior to forming the capacitor storage node forming layer, the removingof at least some of the capacitor storage node forming layer comprisingetching using a chemistry which is substantially selective to remove thecapacitor storage node forming layer relative to the etch stop layer.13. The method of claim 11 wherein the well is substantially planar. 14.The method of claim 11 wherein the semiconductor substrate comprisesword lines having insulative caps and the well has a well base, theremoving leaving a lowest portion of the well base at least 2000Angstroms above the caps.
 15. The method of claim 11 wherein thecapacitors respectively comprise a portion which has a container shape,the portion being formed to be partially received within the wellforming layer beneath the well.
 16. The method of claim 11 comprisingremoving substantially all of the capacitor storage node forming layerfrom within the well after forming the capacitor storage nodeelectrodes.
 17. The method of claim 11 wherein, the capacitorsrespectively comprise a portion which has a container shape, the portionbeing formed to be partially received within the well forming layerbeneath the well; and removing substantially all of the capacitorstorage node forming layer from within the well after forming thecapacitor storage node electrodes.
 18. A method of forming dynamicrandom access memory circuitry comprising: forming an array of wordlines over a semiconductive substrate; forming a substantially planardielectric well forming layer over the word lines; etching at least onewell into the well forming layer which defines a dynamic random accessmemory array area within the well and dynamic random access peripheralcircuitry area laterally outward of well, the well having asubstantially planar base; depositing a dielectric etch stop layer overthe well forming layer laterally outward of and to within the well toless than completely fill the well; forming a dielectric storage nodeforming layer over the etch stop layer laterally outward of and towithin the well to overfill the well; etching an array of capacitorstorage node openings within the well through the storage node forminglayer, through the etch stop layer and into the well forming layer overstorage node contact locations; depositing a capacitor storage nodelayer over the storage node forming layer to within the capacitorstorage node openings to less than completely fill the capacitor storagenode openings; removing the capacitor storage node layer from outwardlyof the storage node forming layer effective to form capacitor storagenode containers within the capacitor storage node openings in electricalconnection with the storage node contact locations, the capacitorstorage node containers having top surfaces received elevationallyproximate an outermost surface of the dielectric etch stop layer; afterforming the capacitor storage node containers, etching the capacitorstorage node forming layer using the dielectric etch stop layer as anetch stop and exposing lateral outer container surface area of thecapacitor containers; forming a capacitor dielectric layer and a cellelectrode layer over the capacitor storage node containers including theouter container surface area of the capacitor containers; and formingthe dynamic random access peripheral memory circuitry laterally outwardof the well.
 19. The method of claim 18 comprising forming the capacitorstorage node containers to have the top surfaces received elevationallyabove the outermost surface of the dielectric etch stop layer by lessthan 50 Angstroms.
 20. The method of claim 18 wherein the dielectricstorage node forming layer is initially formed to be non-planar, andfurther comprising planarizing the dielectric storage node forming layerprior to etching the array of capacitor storage node openings.
 21. Themethod of claim 18 comprising etching substantially all of the capacitorstorage node forming layer from the substrate after forming thecapacitor storage node electrodes and before forming the capacitordielectric layer.
 22. A method of forming dynamic random access memorycircuitry comprising: forming an array of word lines over asemiconductive substrate; forming an array of digit lines over the wordlines; forming a substantially planar dielectric well forming layer overthe word lines and digit lines; etching at least one well into the wellforming layer which defines a dynamic random access memory array areawithin the well and dynamic random access peripheral circuitry arealaterally outward of well, the well having a substantially planar base;depositing a dielectric etch stop layer over the well forming layerlaterally outward of and to within the well to less than completely fillthe well; forming a dielectric storage node forming layer over the etchstop layer laterally outward of and to within the well to overfill thewell; planarizing the storage node forming layer while effectivelyleaving the etch stop layer covered by the storage node forming layer;etching an array of capacitor storage node openings within the wellthrough the storage node forming layer, through the etch stop layer andinto the well forming layer over storage node contact locations;depositing a capacitor storage node layer over the storage node forminglayer to within the capacitor storage node openings to less thancompletely fill the capacitor storage node openings; removing thecapacitor storage node layer from outwardly of the storage nodes forminglayer effective to form capacitor storage node containers within thecapacitor storage node openings in electrical connection with thestorage node contact locations, the capacitor storage node containershaving top surfaces received elevationally proximate an outermostsurface of the dielectric etch stop layer; after forming the capacitorstorage node containers, etching substantially all of the capacitorstorage node forming layer from the substrate using the dielectric etchstop layer as an etch stop and exposing lateral outer container surfacearea of the capacitor containers; forming a capacitor dielectric layerand a cell electrode layer over the capacitor storage node containersincluding the outer container surface area of the capacitor containers;and forming the dynamic random access peripheral memory circuitrylaterally outward of the well.
 23. The method of claim 22 wherein thewell forming layer consists essentially of doped silicon dioxide. 24.The method of claim 22 wherein the well etching leaves the well base atleast 1000 Angstroms above outermost tops of the digit lines.
 25. Themethod of claim 22 comprising forming the capacitor storage nodecontainers to have the top surfaces received elevationally above theoutermost surface of the dielectric etch stop layer by less than 50Angstroms.
 26. Memory circuitry comprising: a semiconductor substrate; aplurality of word lines received over the semiconductor substrate; aninsulative layer received over the word lines and the substrate, theinsulative layer having at least one well formed therein, the wellcomprising a base received over the word lines, the well peripherallydefining an outline of a memory array area, area peripheral to the wellcomprising memory peripheral circuitry area; a plurality of memory cellstorage capacitors received within the well over the word lines; andperipheral circuitry within the peripheral circuitry area operativelyconfigured to write to and read from the memory array.
 27. The memorycircuitry of claim 26 wherein the base is substantially planar.
 28. Thememory circuitry of claim 26 wherein the word lines have insulative capsand the well base has a lowest portion which is received at least 2000Angstroms above the caps.
 29. The memory circuitry of claim 26comprising buried digit lines, the well base having a lowest portionwhich is received at least 1000 Angstroms above outermost tops of thedigit lines.
 30. The memory circuitry of claim 26 comprising burieddigit lines and wherein the base is substantially planar, and the wellbase being received at least 1000 Angstroms above outermost tops of thedigit lines.
 31. The memory circuitry of claim 26 wherein the insulativelayer has a substantially planar outermost surface, and the capacitorshave capacitor storage node electrodes having topmost surfaces receivedelevationally proximate the substantially planar outermost surface ofthe insulative layer.
 32. The memory circuitry of claim 26 wherein theinsulative layer is formed to have a substantially planar outermostsurface, and the capacitors have capacitor storage node electrodeshaving topmost surfaces received elevationally above the substantiallyplanar outermost surface of the insulative layer by less than 50Angstroms.
 33. Memory circuitry comprising: a semiconductor substrate;an insulative layer received over the substrate, the insulative layerhaving at least one well formed therein, the well peripherally definingan outline of a memory array area, area peripheral to the wellcomprising memory peripheral circuitry area, the well having asubstantially planar base; a plurality of memory cell storage capacitorsreceived within the well, the memory cell storage capacitorsrespectively comprising a storage node container which is receivedpartially within the insulative layer through the well base; andperipheral circuitry within the peripheral circuitry area operativelyconfigured to write to and read from the memory array.
 34. The memorycircuitry of claim 33 wherein the word lines have insulative caps andthe well base has a lowest portion which is received at least 2000Angstroms above the caps.
 35. The memory circuitry of claim 33comprising buried digit lines, the well base having a lowest portionwhich is received at least 1000 Angstroms above outermost tops of thedigit lines.
 36. The memory circuitry of claim 33 wherein the insulativelayer has a substantially planar outermost surface, and the capacitorshave capacitor storage node electrodes having topmost surfaces receivedelevationally proximate the substantially planar outermost surface ofthe insulative layer.
 37. The memory circuitry of claim 33 wherein theinsulative layer is formed to have a substantially planar outermostsurface, and the capacitors have capacitor storage node electrodeshaving topmost surfaces received elevationally above the substantiallyplanar outermost surface of the insulative layer by less than 50Angstroms.
 38. Dynamic random access memory circuitry comprising: asemiconductor substrate; word lines received over the semiconductorsubstrate; an insulative layer received over the word lines and thesubstrate, the insulative layer having at least one well formed therein,the well comprising a base received over the word lines, the wellperipherally defining an outline of a memory array area, area peripheralto the well comprising memory peripheral circuitry area, the well havinga substantially planar base; a plurality of memory cell storagecapacitors received within the well, the memory cell storage capacitorsrespectively comprising a storage node container which is receivedpartially within the insulative layer through the well base over theword lines; and peripheral circuitry within the peripheral circuitryarea operatively configured to write to and read from the memory array.39. The memory circuitry of claim 38 wherein the insulative layer has asubstantially planar outermost surface, and the capacitors havecapacitor storage node electrodes having topmost surfaces receivedelevationally proximate the substantially planar outermost surface ofthe insulative layer.
 40. The memory circuitry of claim 38 wherein theinsulative layer is formed to have a substantially planar outermostsurface, and the capacitors have capacitor storage node electrodeshaving topmost surfaces received elevationally above the substantiallyplanar outermost surface of the insulative layer by less than 50Angstroms.
 41. The memory circuitry of claim 38 comprising buried digitlines, the well base having a lowest portion which is received at least1000 Angstroms above outermost tops of the digit lines.
 42. Dynamicrandom access memory circuitry comprising: a semiconductor substrate;word lines received over the semiconductor substrate; bit lines receivedover the word lines; an insulative layer received over the word lines,the digit lines and the substrate, the insulative layer having at leastone well formed therein, the well comprising a base received over theword lines and the digit lines, the well peripherally defining anoutline of a memory array area, area peripheral to the well comprisingmemory peripheral circuitry area; a plurality of memory cell storagecapacitors received within the well over the word lines and the digitlines; and peripheral circuitry within the peripheral circuitry areaoperatively configured to write to and read from the memory array. 43.The memory circuitry of claim 42 wherein the insulative layer has asubstantially planar outermost surface, and the capacitors havecapacitor storage node electrodes having topmost surfaces receivedelevationally proximate the substantially planar outermost surface ofthe insulative layer.
 44. The memory circuitry of claim 42 wherein theinsulative layer is formed to have a substantially planar outermostsurface, and the capacitors have capacitor storage node electrodeshaving topmost surfaces received elevationally above the substantiallyplanar outermost surface of the insulative layer by less than 50Angstroms.
 45. Dynamic random access memory circuitry comprising: asemiconductor substrate; word lines received over the semiconductorsubstrate; bit lines received over the word lines; an insulative layerreceived over the word lines, the digit lines and the substrate, theinsulative layer having at least one well formed therein, the wellcomprising a substantially planar base received over the word lines andthe digit lines, the well peripherally defining an outline of a memoryarray area, area peripheral to the well comprising memory peripheralcircuitry area; a plurality of memory cell storage capacitors receivedwithin the well, the memory cell storage capacitors respectivelycomprising a storage node container which is partially received withinthe insulative layer through the well base; and peripheral circuitrywithin the peripheral circuitry area operatively configured to write toand read from the memory array.
 46. The memory circuitry of claim 45wherein the insulative layer has a substantially planar outermostsurface, and the capacitors have capacitor storage node electrodeshaving topmost surfaces received elevationally proximate thesubstantially planar outermost surface of the insulative layer.
 47. Thememory circuitry of claim 45 wherein the insulative layer is formed tohave a substantially planar outermost surface, and the capacitors havecapacitor storage node electrodes having topmost surfaces receivedelevationally above the substantially planar outermost surface of theinsulative layer by less than 50 Angstroms.